Personal
Next to your laptop
A Thunderbolt device connected to your laptop.
dau runs selected Polars, dataframe, and time-series operations as FPGA dataflow and leaves the rest in software. The same software works with an accelerator next to your laptop or a card in a server.
Hardware
Scans run on the FPGA.
Filters, derived columns, and aggregations stream through tiles built for the workload. Rows can stay in device memory between queries.
Software
Everything else runs in Polars.
If the loaded configuration doesn't cover an operation, it runs on the CPU, and the planner reports what ran where.
Platform
Configurations are assembled from reusable operations and sized to the job. Your code stays the same whether it runs on one accelerator next to a laptop or several cards in a server.
Personal
A Thunderbolt device connected to your laptop.
Scale-out
Several Thunderbolt devices connected to one laptop, with work split across them.
Workstation
A PCIe card in your desktop.
Planned
Several PCIe cards in a server, linked directly to each other.
We measure real workloads to decide what runs in hardware now and what to build next. Every design is verified the same way before it ships.
Results
*On TPC-H query 6, a standard analytics benchmark, adding a dau card to the host made the query about 2.5× faster. The table below lists benchmarks we have run on our boards. Every result matches the software reference exactly.
| Benchmark | Board | Result |
|---|---|---|
| TPC-H query 6, with the table loaded on the card | dpv2 | ~2.5× faster with the card added With a six-million-row table on the card, the CPU and card together finished in 4.2 ms, against 10.4 ms for the CPU alone. The planner picks the split from measured costs. |
| A full day of NYSE TAQ trades turned into OHLCV bars | dpv1 | 137.4M trades, 2.44M bars Every bar matches the CPU Polars result. |
| Time-series workflow: as-of join, derived features, time bars, rolling statistics | dpv2 | 1,024,064 records in 11.5 ms All four steps run in one pass, and intermediate results stay on the card. |
Thunderbolt device
| Parameter | Value |
|---|---|
| Logic | 134K LUTs |
| Memory | 1 GB DDR3 |
| Host link | PCIe Gen2 x2 over Thunderbolt |
PCIe card
| Parameter | Value |
|---|---|
| Logic | 204K LUTs |
| Memory | 2 GB onboard + 8 GB SODIMM DDR3 |
| Host link | PCIe x8 |
| Card cost | About $700 |
PCIe card for servers
| Parameter | Value |
|---|---|
| Memory | DDR4, capacity to be set |
| Host link | PCIe |
| Card to card | Direct fabric links |
Open source
The operator tiles and their reference models, the build system, the simulator, the host driver, and the scheduler are Apache 2.0 licensed and published on GitHub and PyPI. They run on open FPGA hardware, so you can build the same bitstreams we run and add tiles in your own package. Boards built for dau are available through the design partner program. The Polars integration will be released soon.
pip install dau-core dau-driver dau-schedulerDesign partners
We're working with early users on dau hardware, software, and deployment. Tell us what you compute, where it runs, and how fast it needs to be.